Devices for consumer wireless applications require low power and low cost while maintaining sufficient RF performance. Double-polysilicon bipolar processes for RF applications have been demonstrated. Other recently published work has shown that improvements in low power performance can be achieved by scaling the emitter width. Scaling the emitter width provides an additional degree of freedom in the design of low power, low noise amplifiers (LNAs). The noise figure (N.F.) of a LNA is constrained by the transistor base resistance. Typically, a minimum width transistor is chosen and the length is increased until the base resistance drops sufficiently to meet the N.F. specification. Unfortunately low power operation fixes the maximum collector current, so lengthening the transistor decreases collector current density which causes f.sub.T and f.sub.max drop. A narrower emitter reduces the intrinsic portion of base resistance, hence a shorter emitter length is needed to meet the N.F. specification. The shorter emitter length results in higher f.sub.T and f.sub.max at a given collector current.
For the double-polysilicon transistor structure, the emitter width can be reduced by increasing the spacer width. Introducing a wider spacer, however, increases the separation between the emitter and the base polysilicon and requires additional process optimization. A longer extrinsic base drive is needed to address the increase in base link resistance while simultaneously avoiding low breakdown voltage or the increase in emitter-base tunneling current. In addition to disturbing the details of the emitter-base junction, forming a wider spacer involves significant re-optimization of the deposition thickness and etch selectivity of the layers forming the composite spacer. Another conventional method of emitter scaling involves improving the photolithographic tools to print smaller geometries. This path, however, incurs additional equipment cost.